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Advance Data Sheet December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Features
+ + + + + + + + +
Applications
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2.2 GHz operational Dual-band optimized Low supply current (5.1 mA) Surface-mount 14-pin TSSOP package Scaled PD gain for dual-band operation Programmable phase-detector polarity Synchronous or forced counter update loading Powerdown mode via external pin or serial bus Low-load capacitance on reference input buffer
GSM900/1800/1900 North American IS-136/137 Personal Digital Cellular (Japan RCR-27) Personal Handy Phone (Japan RCR-28) CDMA (IS-95)
LD REF_IN R 11-BIT COUNTER TCXO IPD SETTING PD POLARITY IREF M 11-BIT COUNTER PHASE DETECTOR
VDDC
VCP
VCO BAND A
VCO BAND B PRESCALER /64/65 A 7-BIT COUNTER
MAIN_IN
IREF HIGH-PRECISION CURRENT REFERENCE RREF VDDC OFF CHIP
IPD SETTING PD POLARITY BAND
CONTROL LOGIC
24-BIT SERIAL SHIFT REGISTER
LAT DAT CLK
Figure 1. Block Diagram with Pinout
W3000 PLL Dual-Band Frequency Synthesizer
Advance Data Sheet December 1999
Table of Contents
Features...............................................................................................................................................................1 Applications .........................................................................................................................................................1 Description...........................................................................................................................................................3 Pin Information.....................................................................................................................................................4 Absolute Maximum Ratings..................................................................................................................................5 Electrostatic Discharge Caution............................................................................................................................5 Electrical Characteristics ......................................................................................................................................6 Charge Pump Current ..........................................................................................................................................7 PLL Programming Information .............................................................................................................................8 Serial Data Input ..................................................................................................................................................9 Serial Bus Timing Information ..............................................................................................................................9 Functional Descriptions ......................................................................................................................................10 REF Register .....................................................................................................................................................11 MAIN Register....................................................................................................................................................15 PLL Lock-Detect Function ..................................................................................................................................17 Typical Performance Characteristics ..................................................................................................................17 MAIN_IN Input Parallel Equivalent Circuit.......................................................................................................18 Application Example ..........................................................................................................................................18 Application Information ......................................................................................................................................19 Typical Performance Data..................................................................................................................................22 Outline Diagram.................................................................................................................................................26 14-Pin TSSOP................................................................................................................................................26 Manufacturing Information .................................................................................................................................27 Ordering Information ..........................................................................................................................................27
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Advance Data Sheet December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Description
The W3000 is a high-performance UHF RF PLL synthesizer, designed for use in digital wireless communication applications. Particular emphasis in the design has been placed on dual-band applications, with near-seamless switching between operational bands without the need for external loop-filter circuitry other than that required for single band applications. In combination with a suitable reference crystal, UHF VCO, and associated loop-filter components, the W3000 offers a very low-noise oscillator solution. The reference signal is divided by a programmable 11-bit counter to provide a wide range of comparison frequencies, allowing compliance with the various standards. The reference input is rising-edge triggered, and we recommend that an inverting buffer be used when the W3000 is interfaced to a commercial TCXO. The MAIN_IN signal normally associated with the UHF VCO is fed into a dual modulus prescaler (64/65) and is then divided by the 11-bit main counter to be compared to the output of the reference counter in a digital phase detector. The W3000 is implemented with programmable charge-pump currents to allow fast switching between bands for dual-band applications, without changing the loop filter. The charge pump can be programmed internally, or externally with a resistor (recommended). Charge pump outputs can be disabled, thereby allowing open-loop VCO modulation schemes. With synchronous reloading, the counter reloads a new programmed value when the counter reaches zero. With forced counter reloading, the reloading occurs when the programmed word is latched in. These techniques can improve lock time when performing a dual-band hop or in start-up conditions. The W3000 uses a standard 3-wire programming bus (data, enable, clock) that operates up to 10 MHz. This serial interface is via a 24-bit word that incorporates both register addressing and device addressing allowing two chips to share the bus.
TR REGISTER ADDRESS DECODER
CONFIG REGISTER MAIN REGISTER A[0:2] W3020
SC1 LAT CLK SERLE1 SERCK SERDA
PARALLEL LATCH SERIAL SHIFT DAT DAT SERIAL SHIFT CLK LAT
W3000 PARALLEL LATCH A[0:2] ADDRESS DECODER MAIN REGISTER
REF REGISTER
Figure 2. Serial Bus Programming
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W3000 PLL Dual-Band Frequency Synthesizer
Advance Data Sheet December 1999
Pin Information
VDDC CPOUT VSS1 VSS2 MAIN_IN VDD1 VDD2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 LAT DAT CLK PWRDN REF_IN RES LOCKDET
Figure 3. Pin Diagram Table 1. Pin Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol VDDC CPOUT VSS1 VSS2 MAIN_IN VDD1 VDD2 LOCKDET RES REF_IN PWRDN CLK DAT LAT Function Supply Output Ground Ground Input Supply Supply Output Input Input Input Input Input Input Charge Pump Output. Ground 1. Charge pump and logic ground. Ground 2. Prescaler and reference ground. VCO Signal Input. Must be ac-coupled. Voltage Supply 1. Prescaler supply voltage. Voltage Supply 2. Logic and reference supply (must be equal to VDD1). Lock Detect Output. External Resistor Input. Add resistor to VDDC if required (>10 k). Reference Frequency Input. Connection from reference oscillator. Must be accoupled. Powerdown. For low current operation. (Low is powerdown mode.) Serial Input. Programming clock line. Serial Input. Programming data line. Serial Input. Programming latch line. Name/Description Charge Pump Positive Supply Voltage. Must be VDD. (VDD = VDD1 = VDD2).
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Advance Data Sheet December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Ambient Operating Temperature Storage Temperature Lead Temperature (soldering, 10 s) Positive Supply Voltage Positive Charge Pump Supply Voltage Power Dissipation ac Input Voltage Digital Voltages Symbol TA Tstg TL VDD VDDC PD -- -- Min -30 -65 -- 0 0 -- 0 Vss - 0.3 Max 85 150 300 4.5 4.5 250 VDD VDD + 0.3 Unit C C C Vdc Vdc mW Vp-p Vdc
Electrostatic Discharge Caution
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies Microelectronics Group employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500 , capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. Parameter ESD Threshold Voltage ESD Threshold Voltage (corner pins) ESD Threshold Voltage (noncorner pins) Model HBM CDM CDM Min 1000 1000 1500 Max -- -- -- Unit V V V
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W3000 PLL Dual-Band Frequency Synthesizer
Advance Data Sheet December 1999
Electrical Characteristics
Table 2. General Specifications Conditions (unless otherwise specified): VDD = 2.7 V; TA = 25 C 3 C; VREF = 0.25 Vp-p, VDDC = 2.85 V. Parameters Ambient Operating Temperature Nominal Operating Voltage Nominal Charge Pump Operating Voltage Power Supply Current Powerdown Current

Symbol TA VDD VDDC IDD IDD VIH VIL |IIH| |IIL| VOH VOL
Min -30 2.7 VDD -- -- 0.7 * VDD - 0.3 -- -- VDD - 0.4 --
Typ 25 2.85 2.85 5.1 0.1 VDD GND -- -- -- --
Max 85 3.6 3.6 8.0 20 VDD + 0.15 0.3 * VDD 10 10 -- 0.4
Unit C V V mA A V V A A V V
Digital Inputs: Logic High Voltage Logic Low Voltage Logic High Current (VIH = VDD + 0.15 V) Logic Low Current (VIL = -0.3 V) Digital Outputs: Logic High Voltage (|IOH| = 2 mA) Logic Low Voltage (|IOL| = 2 mA)
(IDD1 + IDD2 + IDDC) under locked condition, VDDC = 2.85 V; fVCO.= 1200 MHz; fREF = 13 MHz. (IDD1 + IDD2 + IDDC) VIL = 0 Vdc on all logic input pins.
Table 3. Electrical Specifications Conditions (unless otherwise specified): VDD = 2.7 V; TA = 25 C 3 C; VREF = 0.25 Vp-p, VDDC = 2.85 V. Parameter Main Input Frequency Range Main Input Level (1100 MHz--1750 MHz) Main Input Level
Symbol fVCO VMAIN VMAIN fREF -- -- -- VREF fCOMP -- -- --
Min 0.5 -20 -10 8 20 -- 41 0.25 0.025 10 -2 --
Typ -- -- -- -- 30 1.2 60 -- -- 18 -- -167
Max 2.2 6 6 30 -- 3 -- 2.00 2 -- 2 --
Unit GHz dBm/50 * dBm/50 * MHz k pF mV/ns Vp-p MHz k rad. dBc/Hz
Reference Input Frequency Range Reference Input Shunt Resistance Reference Input Shunt Capacitance Reference Input Slew Rate Reference Input Level Phase Detector Comparison Frequency External Resistor Value (pin 9 to VDDC) Phase Detector Range Phase Detector Noise Floor, 150 Hz offset (25 kHz comparison frequency)
*Equivalent voltage of a 50 terminated source. Frequencies outside the 1100 MHz--1750 MHz range and up to and including 2200 MHz. fVCO = 1190 MHz; VREF = 1.4 Vp-p.
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Advance Data Sheet December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Charge Pump Current
A B C
ICP-DN (T = 25 C ) ICP-UP (T = 25 C )
COMPLIANCE RANGE VDDC - 0.4 V
ICP/mA
D E F
COMPLIANCE RANGE 0.4 V
0.4
A: CP UP CURRENT AT VCP = VDDC - 0.4. B: CP UP CURRENT AT VCP = VDDC/2. C: CP UP CURRENT AT VCP = 0.4.
VDDC/2 VCP
D: CP DOWN CURRENT AT VCP = 0.4 V. E: CP DOWN CURRENT AT VCP = VDDC/2. F: CP DOWN CURRENT AT VCP = VDDC - 0.4.
2.45
Figure 4. Charge Pump Current vs. Voltage Table 4. Charge Pump Specifications Conditions (unless otherwise specified): VDD = 2.7 V; TA = 25 C 3 C; VDDC = 2.85 V; VCP = VDDC/2; RREF = 18 k. Parameter Charge Pump Output Current Conditions ICP = 0.7 mA ICP= 0.7 mA ICP = 0.9 mA ICP = 0.9 mA ICP = 1.9 mA ICP = 1.9 mA ICP = 2.5 mA ICP = 2.5 mA 0.4 < VCP < VDDC - 0.4 V, -30 C < TA < +85 C TA = 25 C 0.4 < VCP < VDDC - 0.4 V, TA = 25 C -30 C < TA < +85 C Symbol IUP IDN IUP IDN IUP IDN IUP IDN ITRI -- -- -- Min 0.6 -0.8 0.8 -1.0 1.6 -2.2 2.1 -2.9 -- -- -- -- Typ 0.7 -0.7 0.9 -0.9 1.9 -1.9 2.5 -2.5 0.1 3 2 8 Max 0.8 -0.6 1.0 -0.8 2.2 -1.6 2.9 -2.1 20 15 8.5 10 Unit mA mA mA mA mA mA mA mA nA % % %
CP High-Impedance State Current CP Sink vs. Source Mismatch CP Current vs. Voltage
2 1
CP Current vs Temperature
3
Notes (refer to Figure 4 for definitions): 1. ICP-DN vs ICP-UP = charge pump output current up vs down mismatch = [|E| - |B|]/[ 1/2 * {|E| + |B|}] * 100%. 2. ICP vs VCP = charge pump output current magnitude variation vs voltage = [ 1/2 * {|F| - |D|}]/[1/2 * {|F| +|D|}] * 100% and [1/2 * {|A| - |C|}]/[1/2 *{|A| + |C|}] * 100%. 3. ICP vs TA = charge pump output current magnitude variation vs. temperature = [|E @ temp| - |E @ 25 C|]/|E @ 25 C| * 100% and [|B @ temp| - |B @ 25 C|]/|B @ 25C| * 100%.
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W3000 PLL Dual-Band Frequency Synthesizer
Advance Data Sheet December 1999
PLL Programming Information
The oscillator frequency is selected according to the following expression: fVCO = where: fVCO = VCO frequency
[(P * M) + A ] * fREF
R
P/(P + 1) = Dual modulus prescaler M
A
= Programmable counter ratio (2 to 2047), M > A = Swallow counter ratio (0 to M - 1 or 127) = External reference oscillator frequency = Reference counter ratio (2 to 2047)
fREF R Example
You wish to have a VCO operating at 1172 MHz, ability to step the frequency in 200 kHz steps, and a reference clock at 13 MHz. Step 1: Calculate the reference counter ratio R R= 13 MHz = 65 200 kHz
Step 2: Calculate M & A fVCO = 1172 =
[(P * M) + A ] * fREF
R
[(64 * M) + A ] * 13
65 1172 * 65 = 5860 13
(64 * M + A ) = 5860 36 = 91 64 64
M is an integer, and so is A; therefore, M = 91, and A = 36.
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Advance Data Sheet December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Serial Data Input
The PLL is programmed via a 3-wire serial bus, utilizing a data pin (DAT), a clock pin (CLK), and a latch pin (LAT).
Serial Bus Timing Information
DAT MSB tCS CLK MSB - 1 tCH LSB
tLL LAT
tCWL
tCWH
tLS
OR
tLWH LAT V
t Figure 5. Serial Bus Timing Diagram
Table 5. Serial Bus Timing Information Symbol tCS tCH tCWH tCWL tLS tLWH tLL fCLK Parameter Data to Clock Setup Time Data to Clock Hold Time Clock Pulse Width High Clock Pulse Width Low Clock Falling Edge to Latch High Setup Time Latch Pulse Width Latch to Clock Setup Time Clock Input Frequency Min 33 10 33 33 0 50 33 -- Typ -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- 10 Unit ns ns ns ns ns ns ns MHz
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W3000 PLL Dual-Band Frequency Synthesizer
Advance Data Sheet December 1999
Functional Descriptions
The W3000 contains a reference register (REF) and a main register (MAIN). The REF register is used for programming the division ratio of the reference clock and for initial setup of the operation modes. The MAIN register is intended for programming that can occur frequently, e.g., dynamic channel switching and putting the W3000 into power-saving mode.
LAT DAT CLK
Both REF and MAIN registers are programmed separately, each with a 24-bit data sequence. The last bit is that which immediately precedes a low-to-high latch input transition occurring while the CLOCK input is low. Bit 24 is loaded first, and bit 1 is loaded last. The last bit in the serial sequence is C0. This bit is used to direct the 24-bit sequence to the MAIN or REF registers. Table 6. C0:C1: MAIN and REF Register Addressing (Destination of Serial Data) (Bits 1 and 24) C1 0 0 1 1 C0 0 1 0 1 Addressed Register MAIN REF Secondary Address Secondary Address
SHIFT REGISTER
ADDRESS DECODER
MAIN
REF
Figure 6. Register Programming Diagram
The first bit, C1, allows the W3000 to share the serial bus. When C1 is a logic high, the W3000 ignores the data sent on the serial bus.
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Advance Data Sheet December 1999
W3000 PLL Dual-Band Frequency Synthesizer
REF Register
This section describes each bit of the reference register. The REF register is used for programming the division ratio of the reference clock and for initial setup of the operation modes. Table 7. REF Register Bit Description (C0 = 1, C1 = 0) Bit 1 2:12 13 14 15:16 17 18:19 20 21 22 23 24 Name C0 = 1 R[1:11] D1 D2 D3, D4 D5 D6, D7 RE ERES EN1 LD C1 = 0 Description Register address bit. C0 = 1 for REF (last bit in serial sequence). Reference frequency divide ratio. Forced counter reload programming (synchronous/asynchronous). Charge pump disable function. Programable charge pump current for frequency band 2. Phase detector polarity. Programable charge pump current for frequency band 1. Reset for first programming after powerup (1 = reset). Enables external resistor (on RES pin) to set charge pump current. Enable W3000. (0 is powerdown.) Lock detect output enable. Secondary address bit (first bit in serial sequence).
Table 8. REF Register Last bit in serial sequence
1 C0 =1 2 R 1 3 R 2 4 R 3 5 R 4 6 R 5 7 R 6 8 R 7 9 R 8 10 R 9 11 R 10 12 R 11 13 D 1 14 D 2 15 D 3 16 D 4 17 D 5
First bit in serial sequence
18 D 6 19 20 21 22 23 24 D RE ERES EN LD C1 7 =0
Table 9. R1:R11: Reference Divider Ratio (Bits 2 to 12) R11 -- 0 0 . . . 1 R10 -- 0 0 . . . 1 R9 -- 0 0 . . . 1 R8 -- 0 0 . . . 1 R7 -- 0 0 . . . 1 R6 -- 0 0 . . . 1 R5 -- 0 0 . . . 1 R4 -- 0 0 . . . 1 R3 -- 0 0 . . . 1 R2 -- 1 1 . . . 1 R1 -- 0 1 . . . 1 Divide Ratio R --* 2 3 . . . 2047
*The reference counter cannot operate with division numbers less than 2.
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W3000 PLL Dual-Band Frequency Synthesizer
Advance Data Sheet December 1999
REF Register (continued)
Table 10. D1: Forced Counter Reload (Bit 13) D1 0 1 Response Synchronous counter reloading update Forced counter reload (M, R, A)
With synchronous reloading, the counter reloads a new programmed value when the counter reaches zero. With forced counter reloading, the reloading occurs when the programmed word is latched in. This can improve lock time when performing a dual-band hop. Table 11. D2: Charge Pump Off Mode (Bit 14) D2 0 1 Response Charge pump enabled Charge pump off (high impedance)
This allows the disabling of the charge pump for systems that directly modulate an open-loop VCO. Table 12. Band and Charge Pump Current (Band 1, Bits 18 and 19; Band 2, Bits 15 and 16) Band 1 1 1 1 2 2 2 2 D3 Bit 15 x x x x 0 1 0 1 D4 Bit 16 x x x x 0 0 1 1 D6 Bit 18 0 1 0 1 x x x x D7 Bit 19 0 0 1 1 x x x x Charge Pump Current ISET 0.7 mA 0.9 mA 1.9 mA 2.5 mA 0.7 mA 0.9 mA 1.9 mA 2.5 mA
The charge pump current is selected by bit 23 of the MAIN register. Setting bit 23 to a 0 will select band 1, which is established with bits 18 and 19 of the REF register. Likewise, setting bit 23 to a 1 will select band 2, which is established with bits 15 and 16 of the REF register. This allows the charge pump current to be dynamically changed along with the VCO frequency. The PLL loop natural frequency is proportional to charge pump current and inversely proportional to the N count. Therefore, when the ratio of charge pump current and VCO frequency is the same, the loop natural frequency does not change. This allows the same loop filter to be used for two different VCO frequencies. For example, in a GSM900/1800 system with VCOs running at 1190 MHz/1570 MHz, the current could be set to 1.9 mA for GSM900 and 2.5 mA for GSM 1800 to compensate for the change in division ratios. The current setting may also be determined by an external resistor. (See Table 15.) In that case, the ratio between the currents programmed will stay the same, but the absolute level will be resistor-dependent.
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Advance Data Sheet December 1999
W3000 PLL Dual-Band Frequency Synthesizer
REF Register (continued)
Table 13. D5: Phase Detector Polarity (Bit 17) D5 0 1 Phase Detector Polarity Negative slope Positive slope
The phase detector can be programmed for either a negative or positive slope to accommodate the VCO and low-pass filter characteristics. (See Figure 7.)
LOOP FILTER W3000 REFERENCE VCO 1 VCO OUTPUT FREQUENCY
0 VCO INPUT CONTROL VOLTAGE
Figure 7. Programming the Phase Detector Slope Table 14. RE: Reset (Bit 20) RE 0 1 Response Operation mode Reset MAIN and secondary registers
After the power supply is turned on, the REF register must be programmed with a reset. This must be followed by a programming of the MAIN register before or at the enabling of the PLL circuit. The RE bit will clear itself, and is required to ensure correct initialization of the IC. This results in the following conditions:
+ + +
The RE bit is cleared back to 0. The device is in powerdown mode, since the EN[1:2] bits are also cleared. Previous reference and main counter values are maintained.
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W3000 PLL Dual-Band Frequency Synthesizer
Advance Data Sheet December 1999
REF Register (continued)
Table 15. ERES: External Resistor Setting for Charge Pump Current (Bit 21) ERES 0 1 External Resistor Status Use internal charge pump current setting (not tested in production) Use external resistor to set charge pump current (recommended)
If bit 21 is set to 0, the W3000 uses its internal current source to set the charge pump currents, with the values shown in Table 12. If bit 21 is set to 1, the charge pump current is set by an external resistor between pin 9 (RES) and VDDC. In this case, the charge pump current is given by the following formula: ICP = ISET * where ICP ISET = Nominal charge pump current. = Current setting as in Table 12. VDDC - 1.05 100 A * RREF
RREF = Value of external current reference resistor. See Table 3 for appropriate value. A tight-tolerance RREF resistor is recommended. Table 16. EN1: Synthesizer Enable (Bit 22) PWRDN (Input Pin 11) High High Low Low EN1 0 1 0 1 Mode Powerdown Enable Powerdown Powerdown
The MAIN register also contains an enable bit, EN2. The W3000 is enabled and powered down with either the REF or the MAIN register, whichever was programmed more recently. The contents of the MAIN and REF registers are maintained in powerdown mode, providing supply voltages are maintained. Table 17. LD: Lock Detect Enable (Bit 23) LD (Bit 23) 0 0 1 1 Mode Disabled Disabled Enabled Enabled PLL Condition Locked Unlocked Locked Unlocked Output Level on Pin 8 LockDet High High High Low
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Advance Data Sheet December 1999
W3000 PLL Dual-Band Frequency Synthesizer
MAIN Register
The MAIN register is intended for programming that can occur frequently for dynamic channel switching and putting the W3000 into power-saving mode. Table 18. MAIN Register Bit Description (C0 = 0, C1 = 0) Bit 1 2:8 9:19 20 21 22 23 24 Name C0 = 0 A[1:7] M[1:11] Reserved Reserved EN2 B C1 = 0 Description Register address bit. C0 = 0 for MAIN (last bit in serial sequence). Swallow counter for prescaler modulus control. Main counter. -- -- Enable all PLL circuits (0 = powerdown mode). Band select for charge pump current control (band 1 = 0, band 2 = 1). Secondary address bit.
Table 19. MAIN Register Last bit in serial sequence
1 C0 =0 2 A 1 3 A 2 4 A 3 5 A 4 6 A 5 7 A 6 8 A 7 9 M 1 10 M 2 11 M 3 12 M 4 13 M 5 14 M 6 15 M 7 16 M 8 17 M 9
First bit in serial sequence
18 M 10 19 M 11 20 X 21 X 22 EN 23 B 24 C1 =0
Note: X bits are don't care bits.
Table 20. A1:A7: Swallow Counter Count (Bits 2 to 8) A7 Bit 8 0 0 0 . . . 0 . . . 1 A6 Bit 7 0 0 0 . . . 1 . . . 1 A5 Bit 6 0 0 0 . . . 1 . . . 1 A4 Bit 5 0 0 0 . . . 1 . . . 1 A3 Bit 4 0 0 0 . . . 1 . . . 1 A2 Bit 3 0 0 1 . . . 1 . . . 1 A1 Bit 2 0 1 0 . . . 1 . . . 1 Counter Ratio 0 1 2 . . . 63 . . . 127
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W3000 PLL Dual-Band Frequency Synthesizer
Advance Data Sheet December 1999
MAIN Register (continued)
Table 21. M1:M11: Programmable Main Counter Divide Ratio (Bits 9 to 19) M11 Bit 19 0 0 . . . 0 . . . 1 M10 Bit 18 0 0 . . . 0 . . . 1 M9 Bit 17 0 0 . . . 0 . . . 1 M8 Bit 16 0 0 . . . 1 . . . 1 M7 Bit 15 0 0 . . . 1 . . . 1 M6 Bit 14 0 0 . . . 1 . . . 1 M5 Bit 13 0 0 . . . 1 . . . 1 M4 Bit 12 0 0 . . . 1 . . . 1 M3 Bit 11 0 0 . . . 1 . . . 1 M2 Bit 10 1 1 . . . 1 . . . 1 M1 Bit 9 0 1 . . . 1 . . . 1 Divide Ratio M 2 3 . . . 255 . . . 2047
The main counter divides the frequency of the prescaler output signal and sources the divided signal to the phase comparator. Table 22. EN2: Synthesizer Enable (Bit 22) PWRDN H H L L EN2 0 1 0 1 Mode Powerdown Enable Powerdown Powerdown
The REF register also contains an enable bit, EN1 (see Table 16). The W3000 is enabled or powered down with either the REF or MAIN register, whichever was programmed more recently. The contents of the MAIN and REF registers are maintained in powerdown mode, providing supply voltages are maintained. Table 23. B: Band Select (Bit 23) B 0 1 Band Band 1 Band 2
In dual-band operation, this bit allows the use of one loop filter by setting the charge pump current to correspond to the frequency of the band selected. See Table 12 for the available charge pump current settings.
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Advance Data Sheet December 1999
W3000 PLL Dual-Band Frequency Synthesizer
PLL Lock-Detect Function
The W3000 provides a basic lock-detect function for fault finding or for system specification requirements. Inside the W3000, the length of the up or down pulses applied to the loop filter is compared with a reference clock period. If the current pulses are shorter than a reference clock period for 15 consecutive comparison periods, the LD line is asserted. If a current pulse is detected that is longer than a reference clock period, the LD line is unset. The LD line gives a signal to indicate a PLL fault condition. It does not provide a true loop-locked output. For example, in a GSM system with a reference clock of 13 MHz and a comparison frequency of 200 kHz, the current pulses only have to be less than 1/65 of a cycle for 15 consecutive times for the LD line to be asserted. This equates to ~0.4 of phase. In the worst case, if the phase stays inside this limit, moving from one extreme to the other, the frequency will only be within 0.2%, i.e., 4 MHz on a 2 GHz VCO. The LD output from the W3000 is a standard logic signal and requires no external comparison or R-C filters.
Typical Performance Characteristics
CURRENT METER VDDC/2
+VDDC 100 pF VDDC CPOUT 442 0.047 F VSS1 VSS2 MAIN_IN 50 +VDD VDD1 VDD2 100 pF UHF SOURCE 10 MHz REF REFERENCE SOURCE LAT DAT CLK PWRDN 0.01 F REF_IN RES LOCK DET RREF = 18 k 50 VDDC C
6.8 pF
Figure 8. MAIN_IN and REF_IN Sensitivity Test Circuit Diagram MAIN_IN and REF_IN are set to cause a small beat frequency at the phase detector input. This generates a sawtooth signal at the charge pump output of known slope. The amplitude of the UHF source is decreased. The sensitivity limit is reached when the slope of this waveform deviates from the calculated value. This is then repeated for the reference source.
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W3000 PLL Dual-Band Frequency Synthesizer
MAIN_IN Input Parallel Equivalent Circuit
The input impedance is high, and can best be represented by the model shown in Figure 9.
Advance Data Sheet December 1999
Table 24. MAIN_IN Input Parallel Equivalent Circuit Values Frequency (MHz) 600 800 1000 C (pF) 0.88 0.87 0.85 0.85 0.86 0.92 1.00 1.10 1.20 R ( ) 3680 2650 2370 1970 1580 1230 740 590 480
MAIN_IN C R
1200 1400 1600 1800 2000 2200
Figure 9. MAIN_IN Parallel Equivalent Circuit
Application Example
VDDC 2.85 V 15 k 3 k 10 nF 1 nF 1 2 3 4 VDDC CPOUT VSS1 VSS2 LAT DAT CLK PWRDN 14 13 C 12 11 1 nF RREF 18 k VDDC
150 pF
5 MAIN_IN 33 pF VCO 33 pF 2.85 V 6 7 VDD1 VDD2
REF_IN 10 RES 9
LOCKDET 8
100 pF 50 50
REF. OSCILLATOR
Figure 10. Application Circuit Diagram
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Advance Data Sheet December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Application Information
A typical PLL system can be modeled as follows:
fREF
1/R
+
KPD
Z(s)
KVCO s
fVCO
1/N
Figure 11. Typical PLL Model KPD = Phase detector in mA/2 rad Z(s) = Loop filter KVCO = VCO gain in MHz/V N R = Total divide ratio = Reference divide ratio
Where the open loop gain is: G(s)OPEN = Where s = j The circuit shown in Figure 12 uses a passive third-order loop filter for the element Z(s), defined by the network:
CHARGE PUMP OUTPUT R1 C1 C2 R2 VCO C3
KPD * Z(s) * Kvco Ns
Figure 12. Third-Order Loop Filter The purpose of the loop filter is to provide response with bandwidth sufficient not only to allow a quick lock time but also to meet phase-noise and reference sideband requirements. Addition of a third pole formed by R2 and C3 will improve reference sideband performance with little overall impact on the loop performance. A reasonable practical limit is that the f comparison is greater than 5 times loop bandwidth.
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W3000 PLL Dual-Band Frequency Synthesizer
Advance Data Sheet December 1999
Application Information (continued)
General rules for the values of these components have been derived many times , and are quoted here merely for reference. If: T1 = T2 = sec - tan p 1 2 c * (T1 + T3)
1
T3 = where
10 attn / 20 - 1 (2 * FREF) 2
= Phase margin required, normally 45 for a critically damped response.
p = Loop bandwidth. c = Loop bandwidth modified for extra pole of R3 and C3, as described by: c =
(T1 + T3) 2 + (T1 * T3 ) * 1+ - 1 (T1 + T3) 2 + (T1 * T3) [tan * (T1 + T3)]2 tan * (T1 + T3)
fREF = Reference frequency. atten = Attenuation provided by the third pole at the reference frequency. The loop filter values can then be derived as:
2 (1 + c * T 2 2 ) T1 KPD * Kvco C1 = * * T2 (1 + c 2 * T12 )(1 + c 2 * T3 2 ) c 2 * N 1/ 2
T2 - 1 C2 = C1 * T1 R1 = T2 C2
The final pole, consisting of R2 and C3, should be chosen such that the following guidelines are followed: C3 C1 and R2 2 * R1 10
1. Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design, Prentice-Hall, 1983.
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Lucent Technologies Inc.
Advance Data Sheet December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Application Information (continued)
For example, take a GSM application where a loop bandwidth of 22 kHz is required. Other parameters specified by the system are listed below: Parameter VCO Gain (KVCO) Charge Pump Current (ICP) Divider Ratio (value of midband frequency used) (N) Required Phase Margin Reference Frequency Attenuation from Additional Pole Value 88 MHz/V 2.5 mA 7850 45 20 dB
Using the formulas above, the three time constants can be calculated as follows: T1 = 2.63697E - 10 T2 = 3.14484E - 10 T3 = 2.38732E - 10 R1 = 2992 C1 = 0.96 nF C2 = 10.5 nF If we choose R2 = 15 k, then C3 = 159 pF From these initial values, the loop filter components used in the application circuit can be derived through practical optimization.
-6 -5 -6
s s s
From these values, we can derive the initial component values as follows:
Lucent Technologies Inc.
21
W3000 PLL Dual-Band Frequency Synthesizer
Advance Data Sheet December 1999
Typical Performance Data
DN (-30 C) UP (-30 C) DN (25 C) 3000 2500 CP CURRENT (A) 2000 1500 1000 500 200 0 0 0.5 1 1.5 2 2.5 3 0 0 0.5 1 1.5 2 2.5 3 APPLIED CP VOLTAGE (V) APPLIED CP VOLTAGE (V) CP CURRENT (A) UP (25 C) DN (85 C) UP (85 C) 1200 1000 800 600 400 DN (-30 C) UP (-30 C) DN (25 C) UP (25 C) DN (85 C) UP (85 C)
Figure 13. Charge Pump Current vs. Voltage and Temperature (2.5 mA)
DN (-30 C) UP (-30 C) DN (25 C) 800 700 CP CURRENT (A) 600 500 400 300 200 100 0 0 0.5 1 1.5 2 APPLIED CP VOLTAGE (V) 2.5 3 UP (25 C) DN (85 C) UP (85 C)
Figure 15. Charge Pump Current vs. Voltage and Temperature (0.9 mA)
DN (-30 C) UP (-30 C) DN (25 C) 2500 UP (25 C) DN (85 C) UP (85 C)
2000 CP CURRENT (A)
1500
1000
500 0 0 0.5 1 1.5 2 2.5 3 APPLIED CP VOLTAGE (V)
Figure 14. Charge Pump Current vs. Voltage and Temperature (0.7 mA)
Figure 16. Charge Pump Current vs. Voltage and Temperature (1.9 mA)
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Lucent Technologies Inc.
Advance Data Sheet December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Typical Performance Data (continued)
SENSITIVITY MAX I/P LEVEL 20
0.5 1.0 2.0
10
0.2
5.0
0 LEVEL (dBm)
VDD = VDDC = 2.85 V
-10
0.0 0.0
0.2
0.5
1.0
2.0
5.0
inf
500 MHz
-20
-0.2
-5.0
-30
-0.5
-2.0 -1.0
-40 0 500 1000 1500 2000 FREQUENCY (MHz) 2500 3000
2.2 GHz
Figure 17. Prescaler Sensitivity and Maximum Input Level
Figure 18. Input Impedance Smith Chart: 0.5 GHz to 2.2 GHz Frequency
TRACE A: -50 dB*
F1 PSD1/K1 A Marker Y* = radrms /Hz
2
1 750.0 Hz
-83.245 dB*
LogMag
10 dB/div
-150 dB*
100 Start: 62.5 Hz RMS: 18.551 mradrms
1k
10 k Stop: 100 kHz Ch1 Carrier: 1.1900005 GHz
100 k
Figure 19. Phase Noise 1190 MHz, Fcomp = 200 kHz
Lucent Technologies Inc.
23
W3000 PLL Dual-Band Frequency Synthesizer
Advance Data Sheet December 1999
Typical Performance Data (continued)
Figure 20. Settling Time from 1150 MHz to 1230 MHz 50 Hz
REF LVL -17.6 dBm -20 -30 -40 -50 -60 -70 -80 -90 -100 -110
DELTA 1 (T1) -78.53 dB 200.40080160 kHz
1
CENTER 1.19 GHz
100 kHz/
SPAN 1 MHz
Figure 21. PLL Reference Spurs
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Lucent Technologies Inc.
Advance Data Sheet December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Typical Performance Data (continued)
Figure 22. Dual-Band Locking
Lucent Technologies Inc.
25
W3000 PLL Dual-Band Frequency Synthesizer
Advance Data Sheet December 1999
Outline Diagram
14-Pin TSSOP
Dimensions are in millimeters.
1.00
7 1
0.19/0.30 1.00 0. 22 0. 03
WITH PLATIN G 1.00 6. 25/ 6.5
0.90/0.135 0.090/0.20
0. 254
M
E
M
BA SE M E T A L DET A IL C
8 14
SEE DETAIL A DET A IL C 0. 65 BSC 1.10 MAX 0.90 0.05
1 0.076 C 5.0 0. 10 0. 15 M AX SEA T IN G PLA N E 4.3/4.5 -E0. 090/ 0.20
0.25 BCS
DET A IL C
8
0.60 0.10 DET A IL A DET AIL G
5-5462 C
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Lucent Technologies Inc.
Advance Data Sheet December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Manufacturing Information
This device will be assembled in multiple locations, which include assembly codes P, M, and T.
Ordering Information
Device Code LUCW3000CCN LUCW3000CCN-TR Description W3000 PLL Frequency Synthesizer Sticks W3000 PLL Frequency Synthesizer Tape and Reel Package 14-pin TSSOP 14-pin TSSOP Comcode 108417601 108417619
Note: Contact your Lucent Technologies Microelectronics Group Account Manager for minimum order requirements.
Lucent Technologies Inc.
27
For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P.R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent T echnologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright (c) 1999 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A.
December 1999 DS99-058WRF (Replaces DS97-268WRF)

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